The most advanced and versatile quad-core, multi-channel ADC
Product status: Active

The first 12-bit ADC to feature a Cross Point Switch (CPS), the EV12AQ600 can operate its four cores simultaneously, independently or paired, to assign its 6.4 GSps sampling speed across the user’s desired channel count:

  • Quad-channel at 1.6 GSps
  • Dual-channel at 3.2 GSps
  • Single-channel at 6.4 GSps

SFDR in 4 channels mode without H2 and H3 harmonics is better than 70 dBFS at -1 dBFS up to 5980MHz.

Learn about multi-ADC synchronization in just 7 minutes

To help you evaluate and design with this ADC, we provide you with the following right here below:

  1. Our growing pack of technical documentation in the download section below.
  2. A high level of free technical support – simply start asking us questions through the form below.

Our customers often praise the quality of our technical support, so don’t hold your questions, send them to us through the form below and let us help you.

This exclusive tutorial video will give you a useful overview of a multi-ADC synchronization technique, from the needs of synchronous and deterministic behavior within a multi-channel system to a practical implementation in our Lab. The demo also features Teledyne e2v’s latest EV12AQ600 ADC.

EV12Q600 Block Diagram


ENOB/SFDR in 4-channel mode
Nyquist Zone Output level ENOB SFDR
NZ1 -1dBFS 8.7 bits 71 dBFS
NZ2 -1dBFS 8.4 bits 63 dBFS
NZ3 -1dBFS 8.1 bits 64 dBFS
NZ4 -8dBFS 8.3 bits 66 dBFS
NZ5 -8dBFS 8.2 bits 67 dBFS


NPR with - 14dBFS loading factor
Nyquist Zone Analog input bandwith selected Channel mode NPR
NZ1 NFPBW 4 44 dB
NZ2 NFPBW 4 43.5 dB
NZ3 EFPBW 4 43 dB
NZ4 NFPBW 1 42 dB
NZ5 NFPBW 1 42 dB
NZ6 EFPBW 1 40 dB


App Notes
Document Description Type
ADX4 IP user guide ADX4 IP user guide for implementation in a Xilinx Kintex Ultrascale FPGA PDF
Application Note AN 21S 218124 Assembly recommendations PDF
Application Note AN 60S 217359 (A) EV12AQ600 Overdrive in Cold Sparing Conditions PDF
Application Note AN 60S 218492 How to improve EV12AQ600 ADC SNR performance using Simultaneous Sampling and Averaging PDF
Design Example ADX4 Design Example User Guide PDF
EV12AQ600 Synchronization Chaining Technical Note SYNCHRONIZATION CHAINING, Simplifying Multi-channel Synchronization in Gigahertz Data Converters. PDF
Document Description Type
EV12AQ600 Datasheet EV12AQ600 / EV12AQ605 Datasheet PDF
Document Description Type
EV12AQ600-2ADC-EVM Synchronization Kit User Guide Multi-chip Synchronization Board with X2 EV12AQ600 + FPGA PDF
EV12AQ600-ADX-EVM Demo Kit User Guide Demonstration Board with EV12AQ600 + FPGA PDF
EV12AQ600-FMC-EVM Development Kit User Guide Development Board with EV12AQ600 + FMC PDF
Document Description Type
EV12AQ600 EV12AQ600 ibis file OTHER
Flyer Product flyer PDF
MIL-PRF-38535 QML Class Y Flow Description of the space flow applicable to EV12AQ600 for non-hermetic flip-chip devices. PDF
Document Description Type
EV12AQ600 Qualification Report PDF
EV12AQ600 TiD and SEE radiation report J710JSG - TiD and SEE radiation Report PDF
Document Description Type
ESIstream white paper ESIstream IP – ease your way to deterministic data serialization PDF

FPGA Support - ESIstream website 


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