Achieving deterministic latency is the topic of discussion in much contemporary systems design today. Past efforts focused on increasing data transmission speeds and bandwidths but increasingly, modern applications now set an equally high value on determinism - the requirement that a data packet be delivered at a precise and repeatable moment in time.
This article considers determinism, at device level and expands on the topic of how ultra-fast data conversion and signal processing systems can be designed to guarantee deterministic latency.
Three factors determine how determinism is achieved as follows:
Action is taken to mitigate against metastable events occurring in digital design elements.
Latency of the digital backend is calculated to ensure alignment of data across multiple data link lanes (e.g., across HSSLs).
Time delay margins are sized to ensure that indeterminism does not appear inadvertently owing to PVT variations.
Specifically, we consider the influence of metastability, its mitigation in synchronous systems and show how to maintain determinism at the interface between analog and the digital signal processing domain.
The ability to manage latencies across a data converter array in ultra-fast systems is critical in complex systems spanning digital beam-steered radar to beam-formed, multi-carrier communications. Latency degrades performance. The engineer’s desire is to bound latency to a known maximum.
Two IC data interfaces do just that: license-free ESIstream and the Industry standard JESD204B (sub-classes 1 & 2). Both are widely used, connecting data converters to logic devices (LD) such as FPGAs and ASICs. Both promise determinism, each differ in specific implementation. The conclusion will show that today, designers have a choice between ultimate flexibility or the low-overhead simplicity and reduced absolute latency of ESIstream.
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